Hello there 👋
I'm Aditya Sood.
I'm Aditya Sood.
I'm Aditya Sood.
MS ECE candidate at Purdue University, passionate about semiconductor design methodologies and crafting seamless hardware-software systems that elevate user experiences.
Projects
DPLL SAT Solver
Spring 2025
Built a SAT solver in Python starting with a basic DPLL algorithm then adding heuristics like DLIS branching, watched literals, and conflict-driven learning. The project showed how each technique improved performance and revealed the trade-offs when scaling to larger benchmarks.
Swipe-Stack
Spring 2024
Lead a design team to re-implement classic Tetris with gesture-based inputs. Proto-typed and designed a PCB for the glove module. Worked on developing embedded C algorithm to calibrate and utilize IMU data to identify correct game inputs.
MIPS Processor
Fall 2023
Implemented register file, ALU, control & request unit within a datapath to execute subset of MIPS assembly instructions. Connected the datapath to memory controller for RAM arbitration. Tested the synthesized design on Altera D2 FPGA.
AHB-Lite USB SoC Module
Spring 2023
Worked in a team of 3 to design and implement 64-byte FIFO & USB Tx/Rx units. The design was then connected to AHB-Lite slave to interface with a given bus-model to achieve 64B payload host-to-endpoint/endpoint-to-host transfers.
Grid Matrix Pathfinder
Spring 2023
Utilized Dijkstra algorithm to create traversal program. Utilized min-heap priority queue & 2D array structures to track runtime data of algorithm. Optimized code to achieve desirable time complexity (<15s) for an input grid of up to 1 million cells.
DPLL SAT Solver
Spring 2025
Built a SAT solver in Python starting with a basic DPLL algorithm then adding heuristics like DLIS branching, watched literals, and conflict-driven learning. The project showed how each technique improved performance and revealed the trade-offs when scaling to larger benchmarks.
Swipe-Stack
Spring 2024
Lead a design team to re-implement classic Tetris with gesture-based inputs. Proto-typed and designed a PCB for the glove module. Worked on developing embedded C algorithm to calibrate and utilize IMU data to identify correct game inputs.
MIPS Processor
Fall 2023
Implemented register file, ALU, control & request unit within a datapath to execute subset of MIPS assembly instructions. Connected the datapath to memory controller for RAM arbitration. Tested the synthesized design on Altera D2 FPGA.
AHB-Lite USB SoC Module
Spring 2023
Worked in a team of 3 to design and implement 64-byte FIFO & USB Tx/Rx units. The design was then connected to AHB-Lite slave to interface with a given bus-model to achieve 64B payload host-to-endpoint/endpoint-to-host transfers.
Grid Matrix Pathfinder
Spring 2023
Utilized Dijkstra algorithm to create traversal program. Utilized min-heap priority queue & 2D array structures to track runtime data of algorithm. Optimized code to achieve desirable time complexity (<15s) for an input grid of up to 1 million cells.
DPLL SAT Solver
Spring 2025
Built a SAT solver in Python starting with a basic DPLL algorithm then adding heuristics like DLIS branching, watched literals, and conflict-driven learning. The project showed how each technique improved performance and revealed the trade-offs when scaling to larger benchmarks.
Swipe-Stack
Spring 2024
Lead a design team to re-implement classic Tetris with gesture-based inputs. Proto-typed and designed a PCB for the glove module. Worked on developing embedded C algorithm to calibrate and utilize IMU data to identify correct game inputs.
MIPS Processor
Fall 2023
Implemented register file, ALU, control & request unit within a datapath to execute subset of MIPS assembly instructions. Connected the datapath to memory controller for RAM arbitration. Tested the synthesized design on Altera D2 FPGA.
AHB-Lite USB SoC Module
Spring 2023
Worked in a team of 3 to design and implement 64-byte FIFO & USB Tx/Rx units. The design was then connected to AHB-Lite slave to interface with a given bus-model to achieve 64B payload host-to-endpoint/endpoint-to-host transfers.
Grid Matrix Pathfinder
Spring 2023
Utilized Dijkstra algorithm to create traversal program. Utilized min-heap priority queue & 2D array structures to track runtime data of algorithm. Optimized code to achieve desirable time complexity (<15s) for an input grid of up to 1 million cells.
Experience
Graduate Lecture TA
Spring 2025 - Now, West Lafayette IN
I serve as a GTA for ECE 362. My duties include overseeing the lecture content including managing homework, conducting help sessions for concept clarification and fostering a holistic understanding of content between the students.
Design-for-Test Intern
Summer 2025, Dallas TX
I explored Cadence Cerebrus to experiment with AI-driven test methodologies. By automating test point insertion experiments, I analyzed trade-offs in coverage, runtime, and memory, gaining insights into both the potential and current limits of AI for scalable chip testing.
Design Verification Intern
Summer 2024, Dallas TX
I developed a utility to model DV codebase dependencies, capturing C preprocessor and linker behavior. I implemented an SQLite database for efficient querying and created a DOT-based visualization tool for dynamic DAG generation, optimizing entire tool-chain to run with just ~2.5% overhead.
Undergraduate TA
Spring 2024, West Lafayette IN
I worked as UTA for ECE 337.
I helped students in RTL design, HDL synthesis, and debugging in a lab setting, guiding them to write parameterized logic for components like shift registers and integrate them into complex designs like serial transceivers and peripheral buses.
Bench Validation Intern
Summer 2023, Dallas TX
I worked as a validation intern in wireless connectivity. The goal of my internship was to develop a new sensor trim algorithm to increase wafer yield and post-FAB performance for temperature sensor in TI's BLE and Sub-1GHz MCU products.
Undergraduate TA
Spring 2023, West Lafayette IN
I worked as UTA for ECE 362. My main duties were helping students in lab in understanding the STM32F091 microcontroller & its onboard peripherals, efficient use of SW4STM32 toolchain for programming & debugging projects in C.
Undergraduate TA
Fall 2021, West Lafayette IN
I worked as UTA for ENGR 131. My main duties were collaborating with GTA in reviewing teaching material before class. I also graded Excel based data analysis assignments and exams while providing key feedback to students for improvement.
Web Design Intern
Fall 2020, Remote
I worked under Chih-Wei Huang with a friend to replace an outdated website with a clean & data efficient design for Android-x86 project - boosting speeds and user retention. I also worked with project leads to secure several new website sponsors for project funding.
Graduate Lecture TA
Spring 2025 - Now, West Lafayette IN
I serve as a GTA for ECE 362. My duties include overseeing the lecture content including managing homework, conducting help sessions for concept clarification and fostering a holistic understanding of content between the students.
Design-for-Test Intern
Summer 2025, Dallas TX
I explored Cadence Cerebrus to experiment with AI-driven test methodologies. By automating test point insertion experiments, I analyzed trade-offs in coverage, runtime, and memory, gaining insights into both the potential and current limits of AI for scalable chip testing.
Design Verification Intern
Summer 2024, Dallas TX
I developed a utility to model DV codebase dependencies, capturing C preprocessor and linker behavior. I implemented an SQLite database for efficient querying and created a DOT-based visualization tool for dynamic DAG generation, optimizing entire tool-chain to run with just ~2.5% overhead.
Undergraduate TA
Spring 2024, West Lafayette IN
I worked as UTA for ECE 337.
I helped students in RTL design, HDL synthesis, and debugging in a lab setting, guiding them to write parameterized logic for components like shift registers and integrate them into complex designs like serial transceivers and peripheral buses.
Bench Validation Intern
Summer 2023, Dallas TX
I worked as a validation intern in wireless connectivity. The goal of my internship was to develop a new sensor trim algorithm to increase wafer yield and post-FAB performance for temperature sensor in TI's BLE and Sub-1GHz MCU products.
Undergraduate TA
Spring 2023, West Lafayette IN
I worked as UTA for ECE 362. My main duties were helping students in lab in understanding the STM32F091 microcontroller & its onboard peripherals, efficient use of SW4STM32 toolchain for programming & debugging projects in C.
Undergraduate TA
Fall 2021, West Lafayette IN
I worked as UTA for ENGR 131. My main duties were collaborating with GTA in reviewing teaching material before class. I also graded Excel based data analysis assignments and exams while providing key feedback to students for improvement.
Web Design Intern
Fall 2020, Remote
I worked under Chih-Wei Huang with a friend to replace an outdated website with a clean & data efficient design for Android-x86 project - boosting speeds and user retention. I also worked with project leads to secure several new website sponsors for project funding.
Graduate Lecture TA
Spring 2025 - Now, West Lafayette IN
I serve as a GTA for ECE 362. My duties include overseeing the lecture content including managing homework, conducting help sessions for concept clarification and fostering a holistic understanding of content between the students.
Design-for-Test Intern
Summer 2025, Dallas TX
I explored Cadence Cerebrus to experiment with AI-driven test methodologies. By automating test point insertion experiments, I analyzed trade-offs in coverage, runtime, and memory, gaining insights into both the potential and current limits of AI for scalable chip testing.
Design Verification Intern
Summer 2024, Dallas TX
I developed a utility to model DV codebase dependencies, capturing C preprocessor and linker behavior. I implemented an SQLite database for efficient querying and created a DOT-based visualization tool for dynamic DAG generation, optimizing entire tool-chain to run with just ~2.5% overhead.
Undergraduate TA
Spring 2024, West Lafayette IN
I worked as UTA for ECE 337.
I helped students in RTL design, HDL synthesis, and debugging in a lab setting, guiding them to write parameterized logic for components like shift registers and integrate them into complex designs like serial transceivers and peripheral buses.
Bench Validation Intern
Summer 2023, Dallas TX
I worked as a validation intern in wireless connectivity. The goal of my internship was to develop a new sensor trim algorithm to increase wafer yield and post-FAB performance for temperature sensor in TI's BLE and Sub-1GHz MCU products.
Undergraduate TA
Spring 2023, West Lafayette IN
I worked as UTA for ECE 362. My main duties were helping students in lab in understanding the STM32F091 microcontroller & its onboard peripherals, efficient use of SW4STM32 toolchain for programming & debugging projects in C.
Undergraduate TA
Fall 2021, West Lafayette IN
I worked as UTA for ENGR 131. My main duties were collaborating with GTA in reviewing teaching material before class. I also graded Excel based data analysis assignments and exams while providing key feedback to students for improvement.
Web Design Intern
Fall 2020, Remote
I worked under Chih-Wei Huang with a friend to replace an outdated website with a clean & data efficient design for Android-x86 project - boosting speeds and user retention. I also worked with project leads to secure several new website sponsors for project funding.
Skills
Digital Design
Programming
Embedded Systems
Hardware
Digital Design
Programming
Embedded Systems
Hardware
Digital Design
Programming
Embedded Systems
Hardware